1. Field of the Invention
The present invention relates in general to a servo control system for a video cassette recorder (VCR), and more particularly to a comb filter for providing accurate servo control of rotation of a drum motor, a rotation control apparatus employing the comb filter and a method of performing a filtering operation utilizing the comb filter.
2. Description of the Prior Art
Generally, in a drum servo control system for a VCR, it has been proposed to minimize factors such as load and rotation variances of a drum motor, resulting in a distortion which has an important effect on a picture jitter. It is the current practice to perform the servo control system based on a software instead of a hardware to minimize the distortion factors still more.
A comb filter has conventionally been proposed to reduce a polarization error in frequency generation and is disclosed in U.S. Pat. No. 4,804,894, assigned to Sony Corporation, Japan. Herein, this comb filter and a rotation control apparatus using the same will hereinafter be described with reference to FIGS. 1 to 6.
Referring to FIG. 1, there is shown a block diagram of the conventional rotation control apparatus. As shown in this drawing, the conventional rotation control apparatus comprises a rotation sensor 2 polarized with magnetic N/S poles to generate a series of frequency generator (FG) pulses as a drum 1 is rotated. The rotation sensor 2 generates six FG pulses whenever the drum 1 is rotated once.
A rotation detector 3 is adapted to detect the six FG pulses and output the detected six FG pulses to a rotation speed error detection circuit 4. In the rotation speed error detection circuit 4, the six FG pulses from the rotation detector 3 are wave-shaped by a control signal generator 41 mid then applied to a speed error counter 42, which counts a time period from a rising edge to a falling edge of each of the wave-shaped FG pulses under control of the control signal generator 41 and converts the resultant counts into digital data.
FIGS. 2A and 2B are waveform diagrams illustrating a series of FG pulses and counts corresponding thereto respectively, and FIGS. 3A to 3D are waveform diagrams of signals from components in the conventional comb filter, designated by the reference numeral 7 in FIG. 1. The wave-shaped six FG pulses as shown in FIG. 2A are sequentially applied to the speed error counter 42. The speed error counter 42 counts a high level duration t1 of the first FG pulse as shown in FIG. 2A and converts the corresponding count N1 as shown in FIG. 2B into digital data D1 as shown in FIG. 3A. Then, the speed error counters 42 counts a high level duration t2 of the second FG pulse as shown in FIG. 2A and converts the corresponding count N2 as shown in FIG. 2B into digital data D2 as shown in FIG. 3A. In this manner, six digital data D1 to D6 are sequentially produced with respect to the one rotation of the drum 1.
If the counts N1 to N6 of the six FG pulses generated as the drum 1 is rotated once are all the same, namely, N1=N2=N3=N4=N5=N6, no error is present in the rotation detection. However, in the actual case, all of the counts N1 to N6 of the six FG pulses are not the same due to a polarization error of the magnetic N/S poles of the rotation detector 3.
Because a series of six FG pulses are generated as the drum 1 is rotated once, the counts N1 to N6 of the six FG pulses of the first series correspond to counts N7 to N 12 of those of the second series, respectively. Namely, the corresponding counts have the same duty factor in polarization.
In other words, the counts N1 to N6 are the same as the counts N7 to N12, respectively. Therefore, a speed error east be detected with no error in the FG detection by accumulating FG deviations of the respective counts and correcting the FG pulses using the accumulated FG deviations.
A differentiator 5 differentiates the speed error digital data D1 to D6 to convert them into angular acceleration error data. It should be noted that a direct current (DC) component of the speed error digital data D1 to D6 is removed while it is differentiated in the differentiator 5 and the angular acceleration error data have an alternating current (AC) component only with no DC component. The angular acceleration error data from the differentiator 5 are multiplied by a multiplication factor K0 by a multiplier 6 and then fed to an adder 8 through the digital comb filter 7 which reduces the error in the rotation detection.
Also, the speed error digital data D1 to D6 are multiplied by a multiplication factor K1 by a multiplier 9 and then applied to the adder 8.
Then, the output data from the digital comb filter 7 and the output data from the multiplier 9 are added by the adder 8, converted into an analog form by a digital/analog (D/A) converter 10 and applied to a motor driver 11, thereby causing the motor driver 11 to control rotation speed of a motor 12.
Referring to FIG. 4, there is shown a block diagram of the digital comb filter 7 in FIG. 1. As shown in this drawing, the speed error data D1 to D6 as shown in FIG. 3A are fed to low pass filters 73 to 78 through an input terminal 71. The speed error data D 1 to D6 are also applied directly to a subtracter 72 through the input terminal 71.
A switch 79 switches selectively the speed error data D1-D6 generated based on the six FG pulses to apply them to the respective low pass filters 73-78 through corresponding contacts P1-P6. A switch 80 switches selectively outputs of the low pass filters 73-78 to apply them to the subtracter 72.
The low pass filters 73-78 have the same construction. Each of the low pass filters 73-78 includes a subtracter 731 having an input connected to a corresponding one of the contacts P1-P6 and an adder 732 having an input connected to an output of the subtracter 731. Each of the low pass filters 73-78 also includes a limiter 733 for limiting a dynamic range of output data from the adder 732, a delay 734 for delaying output data from the limiter 733 for a time period corresponding to the one rotation of the drum 1, a multiplier 735 for multiplying output data from the delay 734 by a multiplication factor K, and a correction circuit 736 for correcting down a decimal point of output data from the multiplier 735.
The output data Da from the delay 734 as shown in FIG. 3B is fed back to the adder 732 and the output data Dg from the correction circuit 736 as shown in FIG. 3C is fed back to the subtracter 731.
The operation of one (for example, 73) of the low pass filters 73-78 with the above-mentioned constructions will hereinafter be described with reference to FIGS. 3A to 3D.
The subtracter 731 obtains a deviation (D1-Dg1) between the speed error data D1 inputted thereto and the output data Dgl fed back from the correction circuit 736 thereto. The adder 732 adds the deviation (D1-Dg1 ) obtained by the subtracter 731 to the output data Dal from the delay 734. The limiter 733 limits the dynamic range of the added data from the adder 732. The delay 734 delays the output data from the limiter 733 for the time period corresponding to the one rotation of the drum 1. As a result, the output data Da1 from the delay 734 represents an average value of the speed error data D1.
The multiplier 735 multiplies the output data Da1 from the delay 734 by the multiplication factor K. The correction circuit 736 corrects down the decimal point of the output data from the multiplier 735. As a result, the correction circuit 736 outputs the data Dg1. The subtracter 72 detects data Dh as shown in FIG. 3D corresponding to a difference between the output at data Dg1 from the correction circuit 736 fed through the switch 80 thereto and the speed error data D1 fed through the input terminal 71 thereto. The operations of the remaining low pass filters 74-78 are substantially the same as that of the low pass filter 73 and details thereof will thus be omitted.
Referring to FIG. 5, there is shown a block diagram illustrating an equivalent circuit of the digital comb filter 7 of FIG. 4 in a digital domain. As shown in this drawing, each of the subtracters 731 and 72 calculates respective differences between the speed error data D1-D6 fed through the input terminal 71 thereto and the output data from the multiplier 735 and applies the resultant data Dh to the adder 732. The output data from the adder 732 is sequentially delayed by six delays Z.sup.-1, multiplied by the multiplication factor K by the multiplier 735 and then transferred to the subtracters 731 and 72. The data Da delayed by the six delays Z.sup.-1 is also fed back to the adder 732. As a result, a transfer function T1 of the digital comb filter 7 in FIG. 5 can be obtained by the following equation (1): EQU T1=(1-Z.sup.-6)/}1-(1-K)Z.sup.-6 } (1)
FIG. 6 is a waveform diagram illustrating a frequency characteristic of the transfer function T1 of the digital comb filter 7. In an NTSC system, a frequency characteristic is required to cut off a frequency (30 Hz) corresponding to 30 rotations per sec. and multiples (60 Hz, 90 Hz . . .) thereof. However, the digital comb filter 7 has a disadvantage in that a low frequency gain is reduced in frequency characteristic.
Namely, the data amount is more rapidly accumulated in the delay 734 as K approximates to 1. As a result, a learning time of the digital comb filter 7 is shortened, whereas the low frequency gain thereof is reduced. In order to compensate for such a low frequency gain, K may become smaller. In this case, the learning time of the digital comb filter 7 is lengthened.
Also, in the case where a constant DC bias component is present in the input to the digital comb filter 7, it may be misrecognized as the polarization error by the digital comb filter 7. In this connection, the digital comb filter 7 has the disadvantage that it performs the learning operation to remove the constant DC bias component.
In order to overcome these problems, Sony Corporation does not dispose the digital comb filter 7 between the speed error counter 42 and a common connection point of the differentiator 5 and the multiplier 9 but at the rear of the differentiator 5, which has a high frequency characteristic, as shown in FIG. 1.
However, although the digital comb filter 7 is disposed between the multiplier 6 and the adder 8 as shown in FIG. 1, the speed error data D1-D6 of the FG cycle are fed to the motor driver 11 through the multiplier 9, the adder 8 and the D/A converter 10, resulting in an effect on the motor 12.
Turning again to FIG. 1, a phase control loop includes a pulse generator (PG) detector 13 for detecting a PG pulse corresponding to the one rotation of the drum 1 and a phase error detection circuit 14 for detecting a phase error in response to the detected PG pulse from the PG detector 13 and a vertical synchronous signal Vp of a video signal. The phase error detection circuit 14 is provided with a control signal generator 141 and a phase error counter 142. The phase control loop also includes a multiplier 15 for multiplying the phase error detected by the phase error detection circuit 14 by a multiplication factor K2 and outputting the result to the adder 8, an integrator 17 for integrating the phase error detected by the phase error detection circuit 14, and a multiplier 16 for multiplying: an output of the integrator 17 by a multiplication factor K3 and outputting the result to file adder 8. The phase control based on the FG pulses has the effect of reducing the error in the rotation detection. However, this results in a problem in which the digital comb filter 7 with the low frequency gain attenuation characteristic as in the above equation (1) cannot be used in a phase control system for the low frequency control.